a Symbol Building and FPGA debugging tool. It is designed for Users who need to automate their symbol building process according to their preferences.
The tool is intended to provide gains in productivity by supporting Table entry form, templates, standard component formats, PDF import, automatic symbols generation,
intelligent data checking and TCL scripting.
Users working with FPGAs will find the tool helpful with checking FPGA signal names against the names of PCB nets on a board
where FPGA is going to be placed. E-Builder supports most of the FPGA devices, processes FPGA constraint files, allows customized symbol generation with FPGA signals names,
places generated FPGA schematic symbols on a page with decoupling capacitors attached, etc.
The generated symbols can be saved to multiple EDA formats the tool supports: Cadence, Mentor, EAGLE, EDIF
supports entering component descriptions using intelligent Table Editor
standard component formats (including BSDL)
supports PDF datasheet processing
compares FPGA signal names to PCB net names of that FPGA on a board.
Symbol Generator allows to place generated schematic symbols on a generated page, do initial wiring, attach decoupling capacitors automtically, etc.
supports all FPGA Vendor formats and most of FPGA devices.
supports all popular schematic symbols formats
has 3 major components:
Table Editor: E-builder's
Table Editor allows to quickly enter component pin descriptions, load standard component formats, import component data from PDF or Excel files, perform intelligent checks and reports
Symbol Viewer/Editor :
Viewer/Editor allows easy navigating between the generated schematic symbols, moving pins between symbols, cross-probing with table of pins.
It can also aoutomatically place symbols on a schematic page with decoupling capacitors attached to specified pins.
E-builder's Comparison tool
can compare FPGA signal names to PCB net names of that FPGA on a board. This allows to find discrepancies if an FPGA pin function doesn't correspond to a PCB net.
Custom rules can be used to influence the comparison process.
FPGA Vendors supported: Xilinx, Altera, Lattice, Microsemi
Schematic formats supported: Cadence's OrCAD Capture, Cadence's ConceptHDL, Mentor's PADS
Powerlogic, Mentor's DxDesigner, Autodesk EAGLE , EDIF 200, EDIF300, etc.
following functions are included with the E-builder tool:
- Building symbols using templates and different Vendor-styles
Interactive editor can work with 2 symbols simultaneously
- Schematic pages generator with built symbols placed on pages and automatic wiring
Comparison wizard to check FPGA package pinout against PCB netlist
- Powerful checker to resolve pin conflicts automatically
- TCL support for automatic symbol creation using scripts
Win7, Win 8.x, Win 10
information please contact our sales department at